ESBF’s 1st Technical Salon
Today, the industry is monopolized by Arm and Intel x86 processor instruction sets. RISC-V, born in University of California Berkeley in 2010, can bring changes to the field to help China’s processor industry to gain control over intellectual property. For embedded systems like consumer electronics and IoT device, RISC-V carries a lot of hype. Today, many universities have adopted RISC-V in courses, major technology companies have started to support RISC-V, and many new business has emerged around RISC-V. Academician Juyan Xu, a well-recognized scholar in semiconductor, pointed out that RISC-V is perfect for “invisible” computing like IoT. RISC-V could find its chance of establishing an ecosystem in China.
With this background, the first ESBF technical salon was about RISC-V in embedded system development. As ESBF secretary in chief Allan He puts it, sharing views, research and experience with RISC-V can help promoting adoption of RISC-V.
New Experiments with RISC-V and RUST
Yu Chen, Associated Professor, Tsinghua University School of Computer Science
While RISC-V appears to be very hardware-specific, Prof. Chen thinks it is actually very software-related. This is because as the layer between hardware and applications, the OS manages the hardware onboard.
According to Prof. Chen, OS courses in different school have different requirements. While some only ask students to become familiar with OS and learn how to use them, many asks for in-depth knowledge of OS. In Tsinghua University, the objective of the course is to teach student to realize an OS design on one particular CPU with a high-level language. In his years of practice, Chen has tried x86, MIPS and arm. In 2017, Prof. Chen found that RISC-V is a very good choice. As an open-source architecture, it originated from a university; technical reference materials are also very easy to obtain (unlike x86 and arm, whose technical details are hard to find).
As for the choice of RUST, Prof. Chen explained that while C is the most common language behind operating systems, it has a lot of safety issues, making it hard to use as a teaching programming language. There are attempts to replace C in OS courses, for example, MIT has tried Go. RUST enforces strict safety boundaries, allows unsafe blocks to be specified, allows runtime boundary check, and in general manages safety problems very well.
After two years of experiment, Prof. Chen has found RISC-V suitable in OS development. One example is that a 32-bit system developed by students can be ported to 64-biy within a day or two; this indicates that RISC-V has considered the problem of software re-usability.
RISC-V in Four-Leg Robotic Design
Linlin Cai, Master’s Candidate, Beijing University of Technology
While it takes more time and efforts before RISC-V become widely adopted in commercial applications, research and applications can be commonly seen in higher institutions. Linlin explained her reasons of selecting RISC-V in her four-leg robotic design project: microcontroller, traditionally used in the control system of a small robot, can experience hardship with complex functionalities due to limited resources; RISC-V, on the other hand, can realize detailed customizations on the processor and enable advanced functionalities.
RISC-V is the Last Chance of China’s Processor Industry
Zhenbo Hu, Founder of Nuclei and well-known RISC-V Promoter
As a well-known RISC-V promoter and the developer of the first RISC-V processor in China, the Hummingbird E203, Mr. Hu has deep and unique views on RISC-V. He thinks that as Moore’s Law and Dennard Scaling law fail, general-purpose processors can no longer achieve the updated requirements of power efficiency; design-specific architecture is now the latest trend and consensus. As system companies and internet giants invest in chip manufacturing, more innovation on hardware-software design has emerged; chip manufacturing starts to exhibit traits of Internet services. Traditionally, Instruction Set Architecture (ISA) serves as the interface between software and hardware. As such architectures are closed, there could be many different programming model/languages present in development for different ISAs, which reduces the efficiency. Due to the fact that an ISA cannot be extended, additions of new hardware cannot benefit from micro-architecture changes. Plus, having to keep developers with different skill sets is a significant cost factor.
RISC-V has four major advantages: simplicity/commonality, no gap between education and industry, openness/extensibility, and high programming efficiency; many of them are pain points of typical embedded system development. The open design of RISC-V makes it able to adapt to diverse requirements in different fields; this strength win support from big companies and the community into the ecosystem. The availability of RISC-V also means more engineers can use it and deploy it into the vast market of IoT.
China has been only a market of processors in the age of x86 and Arm, and has failed to establish its own industry. Hu thinks that RISC-V might be the last change of China’s processor industry. Nuclei focuses on RISC-V processor R&D to on processor IP and solutions; it now offers a lineup of AIoT ultra-low power solutions and is now developing high-performance products with vector acceleration for edge computing. Nuclei is also working hard to extend the market with partners on both ends of the industry chain, hoping to help processors that are made in China to seize the opportunity.
The Key of RISC-V Development Lies in Software and Ecosystem
Lucy Wang, System Engineering Director, NXP China Management Company
With many years of experience in embedded system applications, Wang surely know that engineers need a lot of different resources, from documentation, development tools to hardware reference and reference solutions etc. Software and ecosystem can be the bottleneck of RISC-V’s success in MCUs. NXP, as one of the platinum members of the RISC-V foundation, strives to advance growth of the ecosystem, rather than only producing RISC-V chips.
NXP has established a non-profit RISC-V community for those who are interested in open-source ISA, at www.open-isa.org, released two RISC-V development boards (VEGAboard and VEGAboard Chinese version), and organized several RISC-V design competitions, to help promote RISC-V.
The Familiar Development Environment in RISC-V
Huadong Liu, Senior System Engineer, NXP
From an engineer’s perspective, Liu explained the differences of developing with RISC-V, compared to traditional embedded system development. First, Cmake improves the compilation efficiency (while Arm uses Makefile). Second, debugging software is OpenOCD; a CLI interface is also available for those who are familiar with Linux. As many engineers are used to IAR/Keil environment, the Eclipse IDE environment provides an interface that is close to what engineers have been using.
IAR Can Bridge the Gap of RISC-V Commercialization
Lei Sheng, Country Manager of IAR China
Since IAR is a commercial development tool, it appears that IAR does not intersect with the free open-source RISC-V. However, as a member of the RISC-V foundation, IAR Systems has been involved with RISC-V for three years. In order to commercialize, it is important for a whole system to be advantageous. With only free tools like GCC, RISC-V processors may not compete with Arm on overall system efficiency. For this reason, working with IAR can be fruitful.
Conclusions
We can see that higher education institutions, chip manufacturers and software companies are all holding high hopes for and working hard on RISC-V. We sincerely hope China’s processor industry can take advantage of this opportunity.
The technical salon attracted more than 70 participants from universities, media, and practitioners from several industries, including IC, embedded system, IoT, and industrial electronics. IAR and NXP held live product demo in their interactive sessions.
Embedded System Beijing Forum, which was founded by well-known scholars and industrial practitioners, has recently celebrated 10-year anniversary. ESBF provides a platform for information exchange to experts, scholars, engineers, technicians, marketers, and media personnel. The forum also helps establish personal relationships among the participants. Technical salons are ESBF’s new form of activity designed to appeal to younger and more practical professionals in the audience.
Agenda & Keynotes Download
| Time | Subject | Speaker |
| 1:15-1:25pm | Registration | |
| 1:25-1:30pm | Opening Speech | Yanyong Zhao, Vice Chairman of Beihang University Press |
| 1:30-2:00pm | Operating System Class Lab Session with RISC-V | Dr. Yu Chen, Associate Professor in Tsinghua University School of Computer Science |
| 2:00-2:30pm | RISC-V on FPGA and its Application in Four-Feet Robots | Linlin Cai, Beijing University of Technology |
| 2:30-3:00pm | Characteristics of Embedded System Development with RISC-V | Zhenbo Hu, Founder of Nuclei Technology, Well-known Advocate of RISC-V |
| 3:00-3:30pm | Discussion and Expo | |
| 3:30-3:40pm | NXP and the Development of RISC-V Ecosystem | Lucy Wang, System Engineering Director, NXP China Management Company |
| 3:40-4:10pm | Embedded System Development with RISC-V MCU RV32M1 | Huadong Liu, Senior System Engineer, NXP |
| 4:10-4:30pm | Professional Development Tools that Support RISC-V | Lei Sheng, Country Manager of IAR China |